1. Field of the Invention
The present invention relates in general to non-volatile memories, and more specifically to a system and method for erasing a non-volatile memory using erase ramp pulse width control to reduce erase threshold voltage distribution compression time and hence improve the total erase operation time.
2. Description of the Related Art
During a typical erase operation of a non-volatile memory (NVM) block, such as electrically erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), block erasable EEPROMs (e.g., “Flash” memories), etc., a preprogram procedure is performed to raise the threshold voltages of the memory cells of the memory block to a level at or above a program verify voltage. For the erase operation, the preprogram procedure is followed by a Fowler-Nordheim (FN) erase procedure to lower the threshold voltages of the memory cells of the memory block to a level at or below an erase verify voltage. During the conventional FN erase procedure, however, the resulting distribution may include memory cells which have been over erased, which results in increased column leakage. Furthermore, the problem of column leakage increases as the memory cells are further scaled, causing, for example, a subsequent program operation to fail due to lowered drain bias, or a read operation to fail since the over-erased memory cells may prevent sense amplifiers from distinguishing between an erased cell and a programmed cell. A soft program procedure may be used after the FN erase procedure to compress the distribution of the erased cells so as to reduce the column leakage.
As the technology and feature size of the memory cells become smaller, the total erase operation time has become dominated by the soft programming procedure. In many cases the soft programming has become excessive which resulted in excessive erase time.